1. Field of the invention
The present invention relates to a semiconductor integrated circuit and a method for designing the same. In particular, the present invention relates to a cell-based IC including integrated megacells with a skew adjusting system, and a method for designing the same.
2. Description of the Related Art
It is known that hard megacells such as CPUs, hard macrocells, and standard cell blocks (such as gate array blocks) may be integrated into a semiconductor chip.
The hard megacells are circuit blocks which have an optimized layout design of the semiconductor elements (such as transistors and wiring patterns). They have also been opted to perform their predetermined functions. Further, the finishing process is taken into consideration so as to ensure proper functioning of the hard megacells. Having been previously designed and optimized, the hard megacells may be integrated directly with other components without redesigning the semiconductor elements in the hard megacells because the functions as enabled by the megacells have been previously confirmed through the effort invested in designing the megacell by itself Thus, when attempting to integrate a hard megacell with other devices onto an integrated circuit, the integrated circuit containing hard megacels may be more easily designed (for example, reducing design time required) by incorporating a pre-designed megacell.
Although hard megacells and standard block cells have optimized clock skews in them, clock skews occurs among the megacells, the standard block cells, or each other because of the layout of the cells. If a standard system clock is skewed differently among the various blocks on a chip, the operation of the chip as a whole may be impaired, as the system may not operate at the desired clock rate (by having to wait for each out of phase block to catch up to the operation state of the other blocks).
To solve this problem, independent delay circuits with specific delays have been used to adjust clock skews around a conventional chip.
FIG. 3 shows a block diagram of a conventional semiconductor IC consisting of hard megacells and standard cell blocks which may operate at high speed. The hard megacells and standard cell blocks are referred to as "blocks" hereinafter. The semiconductor IC 58 includes a processor 59, driving hard megacells 60, 61, 62 and a standard cell block 63. A clock signal is supplied to each block through the main clock buffer 7 from a clock input 8. Delay circuits 64, 65, 66, and 67 modify the clock skews based on their locations between the blocks and the delay circuits' internal delay. The delay circuits 64, 65, 66, and 67 are located between the clock input 8 and the clock input to each block in order to arrange the clock skews between the blocks.
The clock tree process is important in the design of the IC chip including the blocks. In the clock tree process, a layout of the blocks is designed so that the clock at the input of each block has the same phase due to calculation of additional influences on the phase of clock skew (such as wiring capacitance or resistance).
FIG. 4 shows a flow chart of a conventional design method for semiconductor ICs. A layout of required hard megacells and standard block cells on a chip is designed (S201). The locations of the wiring lines (wiring of clock and other lines) are determined (S202). After the clock wiring lines for the blocks are designed, the system calculates the clock skew as evident at each block (S203). For example, a difference among the delays of the clock lines is one form of clock skews. According to the result of the calculation of delays at step S203, delay circuits are added in the clock lines to adjust the clock skews (S204). The circuit is redesigned to consider the delay of the additional delay circuits (S205).
Because each block has peculiar delay time and the delay time depends on the layout of the blocks on the chip, it is important to calculate again the whole delay time after the layout of the blocks. The repetitive redesigning of the layout of the blocks and wiring in response to the calculations of the delay times results in an increased design time interval.
Since the conventional method to add delay circuits accounts only for clock skews, the characteristics of the IC may vary due to influences of temperature and from the manufacturing processes. Since the delay circuits are added to fit the skews to the largest delays in the chip, wiring resistance or wiring capacitance are changed due to the addition of the delay circuits. Therefore, adding delay circuits to the previously optimized blocks causes new area to reconfirmation IC operation. These additional reconfirmations increase the design term again. Further, in the instances when the skews cannot be adjusted to accommodate a megacell (for example, more delay circuits cannot be added), the hard megacells must be redesigned. If a hard megacell is redesigned, the design interval again increases as the functions and operations of the cells must be confirmed again.